While choosing a particular digital IC for an application, its specifications or characteristics should be taken into account.
The main specifications for logic families are as follows:
Fanin: The number of inputs that can be connected to a logic gate is called its ‘Fanin’.
Fanout: The number of units that can be connected to the output of a logic gate is called its ‘Fanout’.
CMOS has the highest fanout among the given logic families.
A comparison of the given logic families is as shown:

TTL 
ECL 
CMOS 
FanIn 
1214 
> 10 
> 10 
FanOut 
10 
25 
50 
Power Dissipation (mW) 
10 
175 
0.001 
Noise Margin 
0.5 V 
0.16 V (lowest) 
1.5 V (Highest) 
Propagation Delay (ns) 
10 
< 3 (lowest) 
50 (Highest) 
Noise Immunity 
Very good 
Good 
excellent 
If A and B are the logical inputs to the following circuit, determine the logical relation between the inputs and the output X.
Concept:
Application:
⇒ It can be NOT or NAND (because the output is inversion of input in these two cases)
⇒ NAND Gate (output is inversion of product of both the inputs)
A 
B 
A⋅B 
\(\overline {A \cdot B}\) 
0 
0 
0 
1 
0 
1 
0 
1 
1 
0 
0 
1 
1 
1 
1 
0 
Now,
∴ Output, X = A⋅B
Note:
Most of the students in solving quickly can answer this to be NAND.
As the first part of the circuit given a NAND output but this NAND output is again fed to a circuit whose output is again a NAND operation of its input. That is, NAND operation of a NAND output is AND output.
A particular logic family has V_{OH} = 5 V, V_{OL} = 1 V, V_{IH }= 3.5 V and V_{IL} = 2 V. The noise margin values NM_{H} and NM_{L} will be
Concept:
Noise Margin
It is the amount of noise that can be allowed without disturbing the normal operation of the logic gates.
NM_{low} = V_{IL} – V_{OL}
NM_{high} = V_{OH}  V_{IH}
Calculation:
Given voltage levels are V_{IL} = 2 V V_{OL} = 5 V, V_{OH} = 5 V, V_{IH} = 3.5 V
NM_{low} = V_{IL} – V_{OL} = 2 V – 1 V
NM_{low} = 1 V
NM_{high} = V_{OH}  V_{IH} = 5 V – 3.5 V
NM_{high }= 1.5 V
The most important parameters for evaluating and comparing logic families are:
General comparison of three commonly available logic families is explained in the following table:
Logic Family 
Advantages 
Disadvantages 
CMOS 
Lowest power consumption Used in all microcomputer chips today. Most common logic family. 
Easily damaged by static discharge and voltage spikes. 
TTL 
Earliest developed. Most rugged. Least susceptible to electrical damage. 
Consumes more power than CMOS – not suitable for batteryoperated devices. 
ECL 
Fastest available logic family 
Consumes more power than CMOS. It requires extreme care in the wiring. 
∴ Option 1 is incorrect because the power dissipation in TTL is high and hence CMOS having less waste power as compared to NMOS logic and TTL can be used in highly integrated circuits.
Concept:
The terms positive logic and negative logic refer to two conventions that tell the relationship between logical values and the voltages used to represent them.
1. Logic 0 is always used to represent false and logic 1 is always used to represent true in Boolean Algebra.
2. Positive Logic Convention:
In this, the more positive potential is considered to represent true or logic 1, and the more negative potential is considered to represent false or logic 0.
3. Negative Logic Convention:
In this, the more negative potential is considered to represent true or logic 1, and the more positive potential is considered to represent false or logic 0.
Calculation:
Two voltages are given 2 V and 1 V
As we have to represent them in the positive logic convention:
2 V will represent logic 0 as it is more negative and
1 V will represent logic 1.
Hence option (3) is the correct answer.
Important Points
NMOS uses positive logic Convention
PMOS uses negative logic Convention.
Figure of merit = Propagation Delay × Power Dissipation
For the best IC operation, FOM should be as small as possible.
Units: ns × mW
= pJ (pico Joule)
Propagation delay (tpd):
\({t_{pd}} = \frac{{{t_{PHL}} + {t_{PLH}}}}{2}\)
tPHL = delay time in going form High to low logic
tPLH = Delay time in going from low to High logic
Power dissipation (PD):
PD(avg) = Icc × Vcc
VCC = power supply
ICC = avg collector current calculated as the average of the High and low current, i.e.
\({I_{cc}} = \frac{{{I_{CCH}} + {I_{CCL}}}}{2}\)
Emittercoupledlogic (ECL):
Logic Family 
Full Name 
Advantages 
Disadvantages 
CMOS 
Complementary metaloxidesemiconductor 
1) Lowest power consumption 2) Used in all microcomputer chips today. 3) Most common logic family. 
Easily damaged by static discharge and voltage spikes. 
TTL 
Transistortransistor logic 
1) Earliest developed. 2) Most rugged. 3) Least susceptible to electrical damage. 
Consumes more power than CMOS – not suitable for batteryoperated devices. 
ECL 
Emittercoupled logic 
Fastest available logic family 
Consumes more power than CMOS. It requires extreme care in the wiring. 
Identify the given wiring diagram of ___________.
Joint Box system:
Option 1:
Two lamps controlled by two switches, all connected in series.
S_{1} 
S_{2} 
Bulb 1 
Bulb 2 
OFF 
OFF 
OFF 
OFF 
OFF 
ON 
OFF 
OFF 
ON 
OFF 
OFF 
OFF 
ON 
ON 
ON 
ON 
Option 2:
Two lamps in series, each having switch in parallel
S_{1} 
S_{2} 
Bulb 1 
Bulb 2 
OFF 
OFF 
ON 
ON 
OFF 
ON 
ON 
OFF 
ON 
OFF 
OFF 
ON 
ON 
ON 
OFF 
OFF 
Option 3:
Two lamps each controlled by a separate switch
S_{1} 
S_{2} 
Bulb 1 
Bulb 2 
OFF 
OFF 
OFF 
OFF 
OFF 
ON 
OFF 
ON 
ON 
OFF 
ON 
OFF 
ON 
ON 
ON 
ON 
Output of the circuit shown below when S = 1 and S = 0 will be _____.
Concept:
Complementary Metaloxidesemiconductor (CMOS) uses complementary & symmetrical pair of Ptype & ntype MOSFETS.
Calculation:
As the given figure is of CMOS with two inputs.
The upper part is PMOS which is switched on when 0 is applied and NMOS is switched on when 1 is applied.
Fig A Fig B
1. When S = 0 is applied, the PMOS connected to S (upper one) will be shorted and P at PMOS will appear across the output in complemented form as shown in fig(A).
So Output = P̅
2. Now when S = 1 is applied, the NMOS connected to S (lower one) will be shorted, and due to which ground will appear across the output and the circuit will go in a high impedance state as shown in fig(B).
Hence option (2) is the correct answer.
Option Explanation
Option(1) Schottky transistors are preferred for TTL logic systems. These transistors portray the Schottky effect and thus have higher switching speed in comparison to CMOS logic family.So option 1 is false.
Option(2) TTL dissipates a lot of power where as CMOS uses almost no power in the static state (that is, when inputs are not changing). So option 2 is false.
Option(3) TTL requires more space and isolation in comparison to CMOS logic family. The required silicon area for implementing CMOS is very small. So option 3 is true.
Important Point
1. Characteristics of CMOS Logic Families
2. Characteristics of TTL Logic Families
Concept:
Feature Size: The minimum feature size is the size or the width at which a transistor or any type of material on the silicon surface can be drawn at.
2. If the minimum feature size can be reduced, this means that the transistor length can be reduced effectively making the transistor smaller with the same electrical properties.
3. This allows for lower current flow between the junction for the same purpose and lesser heat dissipation.
The minimum line width is 2 × minimum feature size (1)
Calculation:
Given:
Minimum feature size = 25 μm
Now the minimum line width can be calculated from equation (1)
Minimum line width = 2 × 25 μm
Minimum line width = 50 μm
Hence option (3) is the correct answer.
TTL (TransistorTransistor Logic):
CMOS:
Specifications  TTL  ECL  CMOS 
FAN IN  1214  > 10  > 10 
FAN OUT  10  25  50 
power dissipation (mW) 
10  75  0.001 
Noise margin  0.5  0.16(least)  1.5 (highest) 
Propagation delay(ns)  10  >3  15 
Noise immunity  very good  good  excellent 
Calculate the fan out of a TTL circuit with the following specifications:
I_{OL}(max) = 32 mA, I_{IL}(max) = 1.6 mA, I_{OH}(max) = 400 uA, I_{IH}(max) = 10 uA
Concept:
Fanout
It is the number of Standard loads (input current of the driven gate), the output of a gate to the same logic family.
Fanout high
\(Fanout\;High = \frac{{{I_{OH}}}}{{{I_{IH}}}}\)
Let I_{OH} = 200 μA and I_{IH} = 40 μA
G can drive 5 standard loads.
Fanout low
\(Fanout\;low = \frac{{{I_{OL}}}}{{{I_{IL}}}}\)
Effective Fanout = min (Fanout_{HIGH} , Fanout_{LOW})
Calculation:
Given I_{OL}(max) = 32 mA, I_{IL}(max) = 1.6 mA, I_{OH}(max) = 400 uA, I_{IH}(max) = 10 uA
\(Fanou{t_{HIGH}} = \frac{{400}}{{10}}\)
Fanout_{HIGH } = 40
\(Fanou{t_{LOw}} = \frac{{32}}{{1.6}}\)
Fanout_{LOW} = 20
Effective fanout = min {40, 20}
Effective fanout = 20
Which of the following logic gates can be used to implement the functionality of any logic gate?
Concept:
A universal gate is the one with which any other Boolean function can be implemented without the need of other gates.
Explanation:
Two universal gates are NAND and NOR.
NAND:
In this gate, output of logic gate is false only when both the inputs are true. It is the complement of AND gate.
NOR gate: Output of this logic gate is true when both inputs are false.
Truth Table:
A 
B 
A NAND B 
A NOR B 
0 
0 
1 
1 
0 
1 
1 
0 
1 
0 
1 
0 
1 
1 
0 
0 
Emittercoupledlogic (ECL):
Hence option (2) is the correct answer.
Unipolar Logic Families:
These are classified as:
The output (Y) of the circuit shown in the figure is
Concept:
According to De morgan's theorem:
\(\overline {{A_1}.{A_2} \ldots \ldots {A_n}} = \overline {{A_1}} + \overline {{A_2}} + \ldots \overline {{A_n}} \)
Calculation:
In the given circuit, signals A, B, and C̅ are in series for NMOS implementation. ∴ The output will be:
\(\left( Y \right) = \overline {A.B.\bar C} = \bar A + \bar B + C\)
Propagation delay:
It is the time required for a digital signal to travel from the input(s) of a logic gate to the output ad is denoted by (tpd)
In the case of a digital IC, the propagation delay of a gate is the average transition time that a signal takes from input to output, i.e.
\({t_{pd}} = \frac{{{t_{PHL}} + {t_{PLH}}}}{2}\)
Units – ns (nanoseconds) i.e. 109 sec
Speed of operation is related to the propagation delay, so, it is advantages to have smaller tpd’s
Family 
tpd (ns) 
MOS 
70 
TTL 
10 
RTL 
12 
ECL 
2 
Among the given options, TTL has the least propagation delay.
The logic function f(X,Y) realized by the given circuit is
Concept:
CMOS logic circuit is an extension of a CMOS inverter. It consists of two network transistors, a pulldown network (PDN) constructed of an nMOS and Pullup Network (PUN) constructed of PMOS.
PDN: Since nMOS conducts when the signal gate is high, PDN is activated when the inputs are high.
PUN: It comprises PMOS and conducts when the input signal gate is low.
The PDN and PUN are connected in parallel to form OR logic function and they are connected in series to form AND logic as shown:
Application:
\(\overline {{\rm{\bar x}}.{\rm{\bar y}} + {\rm{xy}}} = \overline {{\rm{x}} \odot {\rm{y}}} \) = x ⊕ y = XOR
The above circuit acts as:
Explanation:
Inverter
This is equal to NOT gate in the digital circuitry.
The output of this is a compliment of the input.
This can be built from the transistors like BJT, MOSFET, etc…
The CMOS inverter consists of the NMOS and the PMOS fieldeffect transistors connected in one below the other.
When In = Low
PMOS will be shorted and output will be High.
When In = High
NMOS will be shorted and output will be Low.
Hence it acts as an inverter.
Important Points
The structure with the BJT when acting as inverter is: